1. Field of the Invention
The present invention relates to an information processing apparatus, in particular, an information processing apparatus that supplies and executes a plurality of instructions as a single instruction group.
2. Description of the Related Art
With the proliferation of multimedia in ordinary households in recent years, there has been an increasing demand for improved performance of processors that perform image processing and sound processing. Accordingly, parallel processing techniques have been employed in an attempt to speed up processors. For instance, processors that execute SIMD (Single Instruction stream Multiple Data stream) instructions exist as an example of data-level parallel processing technique. Also, VLIW processors (Very Long Instruction Word Processors) exist as an example of instruction-level parallel processing technique. Further, in order to perform parallel processing in the temporal direction, a technique has been employed in which the number of pipeline stages is increased to improve the processor's operating clock frequency.
Of these techniques, a VLIW processor achieves enhanced parallelism by simultaneously executing a plurality of instructions contained in a single instruction group (VLIW instruction), thereby improving processor performance. For example, four processes are specified in a single instruction group and executed in parallel, thereby enabling high speed computation processing. Also, this VLIW processor uses an instruction that designates repetition of a process when the same process is to be performed on a plurality of pieces of data, thereby removing instruction code repetitions for improved code efficiency. For example, in the related art, there is a repeat instruction that repetitively executes a process within a repeat block (see, for example, Japanese Unexamined Patent Application Publication No. 2002-229779 (FIG. 15)).